PLC scan cycle and process image

What a PLC scan cycle consists of, what the input and output process images are, cycle time and its monitoring, and what this means for your program.

The cycle

A classic PLC executes its program cyclically. The Siemens S7-1500 manual defines a cycle as:

  1. Reading the input modules into the process image input (PII).
  2. Executing the cyclic program (OB 1 on Siemens).
  3. Writing the process image output (PIQ) to the output modules.

Then the cycle repeats. The operating system measures the time of each cycle.

Process image

The program does not work with the terminals directly but with a copy of the inputs taken at the start of the cycle. Therefore:

  • during a cycle an input value does not change, even if the terminal signal did — the logic sees a consistent snapshot;
  • outputs physically switch only at the end of the cycle; intermediate assignments to the same output never reach the outside — the last one wins;
  • a pulse shorter than one cycle may be missed — fast signals need hardware interrupts, high-speed counters or modules with edge latching.

Most PLCs allow direct peripheral access (on Siemens %IW100:P) bypassing the image, but that is an exception for special cases.

Cycle time

Cycle time is not constant: it depends on program branches, interrupt handling and communication. S7-1500 defaults:

ParameterDefaultPurpose
Minimum cycle time1 msevens out cycle time, leaves time for communication
Maximum cycle time150 msdetects a hung program

When the maximum is exceeded, OB 80 (time error) is called; if it is not loaded, or the cycle still hasn't finished after another interval, the CPU goes to STOP. Every PLC has a similar watchdog; only the settings and reactions differ.

What this means for your program

  • Never wait inside a cycle. WHILE loops waiting for an event block input updates and trip the watchdog. Waiting is done with a state and a timer checked every cycle.
  • One write per output. Several assignments to the same variable in different places are a common source of bugs: the last one wins. The static analyzer flags this as multiple writes.
  • Edges are detected by comparing with the previous cycle — see timers, counters and edges.
  • System response time is up to two cycles plus module and network delays: an event may happen just after the inputs were read.
  • For controllers and fast tasks use cyclic interrupts with a fixed period (OB 30…38 on Siemens, separate tasks in CODESYS/TwinCAT).

Tools

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Sources

  1. SIMATIC S7-1500 Cycle and response times — Function Manual 02/2014 — Siemens AG
  2. PLCopen — IEC 61131-3 — PLCopen

Updated 2026-10-01